OctEval: Microelectronic Test Structures

Integrated approach to design, test and characterization of test structures for microelectronic technologies

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Contact: mbhushan@octeval.com

 Reduce technology development and manufacturing costs by

• Designing and implementing compact and effective microelectronic test structures for technology development and manufacturing
• Avoiding common errors in test structure design that lead to ambiguous results
• Integrating design methodology with test and data acquisition for rapid feedback
• Rendering data in a clear and concise manner

Electrical test structures are an essential part of fabrication technologies, whether in a small-scale research laboratory or a multi-billion dollar silicon foundry. As microelectronic technologies become more complex and expensive, test structures play a critical role in reducing time to maturity and the cost of development and manufacturing.

Dr. Manjul Bhushan has many years of broad, hands-on experience in the area of microelectronic test structures and experimental design. She worked with IBM's 180 nm to 32 nm CMOS technology nodes, as well as in photovoltaics and superconducting technologies earlier in her career. Key elements of scribe-line test structures for CMOS technology are presented in the book entitled

"Microelectronic Test Structures for CMOS Technology"

A comprehensive guide to serve as a handbook for professional engineers and engineering students engaged in design, test and statistical data analysis for CMOS technology characterization.
  Authors: Manjul Bhushan and Mark B. Ketchen
  Springer, published August 2011. Available in hardcover and ebook

Recently (2015 - present), Dr. Bhushan has been actively involved in designing test structures for technology and performance evaluation of superconducting single flux quantum (SFQ) circuits. Inspired by her earlier work in CMOS technology evaluation, these test structures bring a disciplined methodology to model-to-hardware correlation in this field with potential applications in digital electronics including control circuitry for superconducting quantum computors.

Selected Publications:

1. ERSFQ power delivery: a self-consistent model/hardware case study
Ketchen MB, Timmerwilke J, Gibson GW, Bhushan M (2019).
IEEE Trans Appl Supercond 29:7; DOI: 10.1109/TASC.2019.2907690
2. Silicon technology inspired test structures and methodology for SFQ model-to-hardware correlation
Bhushan M, Timmerwilke J, Amparo D, Gibson GW, Ketchen MB (2019).
IEEE Trans Appl Supercond 29:5; DOI: 10.1109/TASC.2019.2898410
3. High speed test structures for in-line process monitoring and model calibration
Ketchen MB, Bhushan M, Pearson DJ (2005). Proceedings of the 2005 IEEE international conference on microelectronic test structures, 2005, pp 33-38. Best paper award
4. Ring oscillator based technique for measuring variability statistics
Bhushan M, Ketchen MB, Polonsky S, Gattiker A (2006). Proceedings of the 2006 IEEE international conference on microelectronic test structures, 2006, pp 87-92. Best paper award
5. CMOS latch metastability characterization at the 65-nm-technology node
Bhushan M, Ketchen MB, Das KK (2008). Proceedings of the 2008 IEEE international conference on microelectronic test structures, 2008, pp 147-151